module divider(clkin, res, clkout1, clkout2, dig0, dig1);
input  clkin, res;
output clkout1, clkout2, dig0, dig1;

wire clkin, res, clkout1, clkout2, dig0, dig1;
reg [15:0] cnt;

always @ (posedge clkin or posedge res)
begin
  if (res)
    cnt = 16'h0000;
  else
    begin
       if (cnt == 16'h7a11) //12'h9ff
         cnt = 16'h0000; 
       else
         cnt = cnt + 1;    
    end
end
assign clkout2 = cnt[14];
assign clkout1 = cnt[13];
assign dig0 = cnt[7];
assign dig1 = cnt[8];
endmodule

//====================================================================================

module decade_counter(clk, res, outp, ov);
input  clk, res;
output [3:0] outp;
output ov;

wire clk, res;
reg [3:0] outp;
reg [3:0] cnt;
reg ov;

always @ ( posedge clk or posedge res)
begin
  outp = 0;
  ov = 0;
  if (res)
     begin
	outp = 4'b0000;
	ov = 1'b0;
	cnt = 4'b0000;
     end
  else
     begin
        cnt = cnt + 1;
	ov = 1'b0;
	if (cnt == 4'd10)
          begin 
            cnt = 4'd0;
	    ov = 1'b1;
          end
        outp = cnt;
     end	 
end
endmodule

//========================================================================================

module latch(data_in, clkp, ldata_out);
input  clkp;
input [3:0] data_in;
output [3:0] ldata_out;

wire clkp;
wire [3:0] data_in;
reg [3:0] ldata_out;

always @ (posedge clkp)
  begin
    ldata_out <= data_in;
  end
endmodule

//========================================================================================

module mux(sel1, sel2, data1_in, data2_in, data3_in, data4_in, mxdata_out);

input sel1, sel2;
input [3:0] data1_in, data2_in, data3_in, data4_in;
output [3:0] mxdata_out;

wire sel1, sel2;
wire [3:0] data1_in, data2_in, data3_in, data4_in, mxdata_out;

assign mxdata_out = ((sel2 == 1'b0) && (sel1 == 1'b0)) ? data1_in : 
                    ((sel2 == 1'b0) && (sel1 == 1'b1)) ? data2_in :
		    ((sel2 == 1'b1) && (sel1 == 1'b0)) ? data3_in : data4_in;
endmodule

//==========================================================================================

module bcd2ss(inp, ss_out);
 
input [3:0] inp; 
output [6:0] ss_out;
wire [3:0] inp;
wire [6:0] ss_out;

assign ss_out =  (inp == 4'd0) ? 7'b0111111 :  //0
		 (inp == 4'd1) ? 7'b0110000 :  //1 
		 (inp == 4'd2) ? 7'b1101101 :  //2
		 (inp == 4'd3) ? 7'b1111001 :  //3
		 (inp == 4'd4) ? 7'b1110010 :  //4
		 (inp == 4'd5) ? 7'b1011011 :  //5
		 (inp == 4'd6) ? 7'b1011111 :  //6
		 (inp == 4'd7) ? 7'b0110001 :  //7
		 (inp == 4'd8) ? 7'b1111111 :  //8
		 (inp == 4'd9) ? 7'b1111011 : 7'b1000000; //9 : default

endmodule

//============================================================================================

module dec2to4(data_in, data_out);

input [1:0] data_in; 
output [3:0] data_out;
wire [1:0] data_in;
wire [3:0] data_out;

assign data_out = (data_in == 2'd0) ? 4'b0001 :  //dig1
		  (data_in == 2'd1) ? 7'b0010 :  //dig2
		  (data_in == 2'd2) ? 7'b0100 : 7'b1000; //dig3:default dig4					   
endmodule