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7.7 voltage controlled oscillator
□ O voltage controlled oscillator (Voltage-Controlled Oscillator, VCO) is a circuit that generates a square triangular waveform whose duration, frequency and thus regulated by a dc voltage (control).
A typical oscillator VCO is the integrated circuit 566, which contains circuits that generate both rectangular and triangular pulses whose frequency is defined primarily by an external capacitor C1 and an external resistor R1, and is influenced by a dc input voltage VC. The Sch.7.15 shows the block diagram of the integrated 566, a simple setup ¬ generates three functions, as well as terminals. As seen from the shape, consists of 566 sources / power generators, a stimulator of Schmitt and two amplifiers / buffers. Generators power and charge the external capacitor ekfortizoun C1 at a rate determined by the external resistor R1 and the form dc input voltage (or control) VC. The stimulator Schmitt used to make switching between power sources to charge and discharge the capacitor voltages and between the exit buffer, ie the triangular waveform developed at the ends of the capacitor and the square wave coming from the exciter Schmitt.
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Shape control voltage input
Power sources
Stimulator Schmitt
Amplifiers / Isolators
input voltage Vi 5 configuration
Figure 7.15. Block diagram of the VCO 566 function generator or
and terminals
The oscillation frequency of the central operating frequency f0, sub-
be from the relationship:
(7.7.1)
with the following practical limitations:
1. The R1 should be in 2kQ <R1 <20 kQ
2. The VC should be in the area (3/4) VCC <VC <VCC.
3. The f0 should be below 1 MHz.
4. The VCC must be between 10 and 24 V.
10.4)
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The Sch.7.16 syndesmologimeno 566 shows as a regulated function generator gives us simultaneously square and triangular pulses with constant frequency determined by R,, C1 and VC. The voltage control or modulation VC, and therefore the frequency of the waveform, f0, is regulated at will through the voltage divider R2, R ^
Figure 7.16. To 566 as a regulated generator, square and triangular waveforms
Example 7-6
If the circuit is Sch.7.16: R, = 10 kO, R2 = 1.5 kO, R3 = 10 kO, C, = 820 pF and VCC = 12 V, to find the control voltage VC and the oscillation frequency of the output waveform of.
Solution
From the voltage divider R2, R we have
when Eq. (7.7.1) gives
Solution
When the middle taking the potentiometer is at the top of,
we have:
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The Sch.7.17 shows how most can adjust the frequency of the square of triangular pulses using variable voltage VC, to alter the frequency f0. The median download metatakineitai potentiometer R3 in the full range of 10:1.
Figure 7.17. Syndesmologisi the VCO 566 as a unit
Example 7-7
If the circuit has Sch.7.17 values R1 = 10 kO, R2 = 470 O, R3 = 5 kO, C1 = 220 pF, R4 = 18 kQ and VCC = 12 V, to find the two extreme possible oscillation frequencies, depending on the position of the potentiometer.
So,
Analogue Electronics
When the middle taking the potentiometer is in the down position, we will:
So
7.7.1 O VCO for Frequency Modulation
Rather than alter a potentiometer to change the voltage VC, we can apply to an input voltage v shape, as shown in Sch.7.18 where VC = Vdc + v In this figure the voltage divider voltage VC generates around 10 V, with polarization Vdc = 10.4 V. A (superimposed) ac input voltage around 1.4 V (peak value) makes the voltage VC to change from 9 V to 11.8 V, forcing the output frequency to vary, respectively, over a dynamic range 10:1. Therefore the input signal v will define the output in the frequency around a center frequency f0 which is determined by the value of the polarization Vdc = 10.4 V (f0 = 121.2 KHz).
Figure 7.18. Operating the VCO input voltage shape with frequency modulation for
The center frequency f0 of the VCO
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To VCO is used to convert synchna very low frequency signals such as those taken in electroencephalograms (EEG) and electrocardiograms (EKG), a frequency modulated signals belonging to the audio frequency range. The acoustic signals are then can be transmitted over telephone lines for diagnosis (telemedicine) purposes or can be recorded on a magnetic medium for further processing.
7.8 Loop clavicle phase
O clavicle loop phase (Phase Locked Loop, PLL) is a flexible electronic circuit of observation frequency or phase waveform consists of a comparator or phase detectors (PC), a low frequency filter (LPF) and a voltage controlled oscillator (VCO ) connected as shown in Sch.7.19.
Figure 7.19. Block diagram of the clavicle phase loop (PLL)
Typically, the comparator or phase detectors compare the input frequency f the frequency of the VCO f0 as follows: The output of the phase detectors is proportional to the phase difference of signals vi and v0. The output voltage of the phase detectors is a dc voltage is called voltage error (ve). The output of the phase detectors applied to the FSF, which suppresses the high frequencies (fi + f0) and creates a clean dc
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trend. This dc voltage in turn is the entrance to the VCO. Since the VCO output frequency is proportional to the dc input level, the frequency of the VCO is made equal to the input frequency.
Overall, the loop phase clavicle goes through three states: self-excitation, phase arrest and clavicle. Before applying the input signal, the loop phase clavicle is the self-excitation condition. When applied to the signal input frequency or the frequency of the VCO starts to change and in this case the loop phase clavicle in the situation warrants. The VCO frequency continues to change until they become equal to the input frequency and then the loop phase clavicle has entered the state clavicle phase. When the phase locked loop monitor any change in the input frequency by repetitive action.
Because the PLL circuit does not require reactors ¬ manufactures its easy to form an integrated circuit. The most common of these circuits clavicle loop phase is the chip PLL 565. The Sch.7.20 shows the block diagram of this integrated and the base together with the akrodeketes.
FTT (LPF)
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Phase comparators
On. apodiamorf. 7
Figure 7.20. Structural phase diagram of clavicle loop PLL 565
The most important features are:
1. Area of operation frequency: 0.001 Hz to 500 kHz.
2. Voltage operating range: ± 6 V to ± 12 V.
3. Input level: 10 mV rms to 3 V pp.
4. The resistor R1 should be between 2 and 20 KO KO.
The center frequency of the PLL frequency is determined by self-
stimulation of the VCO, which for the PLL, it is given by:
/ = 0
Hz
(7.8.1)
where R1 and C1 are external components connected to terminals 8 and 9, respectively. The self-excitation frequency f0 is set externally by the elements R1 and C1, that is to the center frequency of the input. O capacitor C2 must be large enough to eliminate the fluctuations of the output voltage and thus stabilize the frequency of the VCO.
The PLL 565 is locked and can detect a signal within a range ± 60% of the transit frequency range, as the center frequency f0. The clavicle area and the region fL fC arrest of this PLL is given by the following relations:
(7.8.2)
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where f0 is the frequency of self-excitation of the VCO (in Hz) and
(7.8.3)
where R2 is O and C2 in F, while the f in Hz.
On. apodiamorf.
Figure 7.21. The 565 syndesmologimeno as frequency modulation circuit
To PLL circuit is an important as a basis for a range of applications. Used for frequency modulation (FM), for frequency synthesis and multiplication and division frequencies. Also, the PLL is used as a decoder, DPI (Frequency-Shift Keyed).
Example 7-7
For the circuit of Sch.7.21, find the self-excitation frequency f0, fL clavicle area and the area arrest fC.
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Solution
From Eq. (7.8.1) (7.8.2) and (7.8.3) we have:
