Lesson 3.8 Data Transfer Techniques
Regular scanning mode (Polling)
Operation Holiday
DMA (Direct Memory Access)
By studying the lesson you will
to know the function of Polling
to know the functioning of the holiday
know what is DMA
3.8.1 Contact Devices with the processor
In previous lessons describe the ways in which the processor communicates with memory and the peripheral units. This course will look at techniques that regional units alert the processor that need to communicate with him.
Suppose we have a keyboard plugged into a computer system. The keyboard is an input unit. Each time you press a button has the keyboard to communicate with the editor and tell which key was pressed. The time, however, moments in which we press one button is random. The processor does not know when to expect keystroke you have to wait. If the processor then looks at the keyboard if a key is pressed then it will not be running any other program simultaneously. We are constantly busy monitoring the keyboard
A simple technique used to solve this problem in computing is just the regular scanning technique (polling). Suppose we have four input devices, connected to a computer system. (Figure 3.8.1) According to this technique, the processor checks at regular intervals every input, if it has something to "say". That is a control signal input to each unit of "telling" if it is enabled. This mark indicates that the unit has data to be sent to the processor. In this way the processor can run a program and at regular times interrupts the execution of the program and looking one by one peripheral devices if they have a new fact. As shown in Figure 3.8.1, the processor looks at the first unit 1 if new data. If it serves the unit 1, and otherwise looking unit 2. This process continues until you check all four units. Usually the input modules are slow devices. Take for example the plitrologio and suppose that we can plitrologoume 10 keys per second. At this rate the keyboard activates a signal indicating that it has new data every 100 msec. Today a simple processor with an operating frequency of 20MHz can execute about 100,000 orders in the period of 100 msec. From this example we understand that the processor can execute a program and at regular intervals to check the input modules without any problem. So if you check every 100 msec has 100,000 available commands. A small number of them (~ 10 orders) are sufficient for control. The rest can be used by the program running.
Figure 3.8.1 Control units with Polling
The advantage of this technique is that the design of the computer system is quite simple and the program needed to run the processor is easy to design and implementation.
The disadvantages are that the servicing of the units is input through the program and not the material. This means that every time we want to incorporate a new device we need to change the whole program of the processor. Another serious drawback of this technique is that we lose a lot of time when the processor halts execution of the program to control all peripheral devices. Most times the processor finds no new data to all devices so the time it takes to check the devices to be lost by the time of execution of the program. Finally, this technique works well only for slow devices.
3.8.2 Holidays
Another widely used technique to communicate the input unit with the processor is on holiday (interrupt).
According to this technique, the processor must have an input signal with which to notify at least one outdoor unit wants to communicate with him. The processor each time a command is executed facing the mark. This is done through the program but is embedded in the processor hardware automatically with each command is executed. So the rate at which the processor understands when a new external drive has given very high (at the end of each command), so it can serve and respond to requests (vacation) fast devices.
When the processor recognizes the need to accommodate an input unit, temporarily stops the execution of the program starts running and servicing the unit. When finished servicing the unit returns to the program executed and continues from where it stopped. The interrupt signal that controls the processor called INTR (interrupt request - interrupt request). The signal this sends the device requesting service. When the processor is ready to serve the device requesting service, enables the identification mark off INTA (interrupt ack). The device expects the INTA signal processor and are activated as soon as the processor and the device for data transfer.
Figure 3.8.2 Signals holiday
Of course, there are actually more than one peripheral device to a computer system. Each one of them sends its own interrupt signal in a circuit called a programmable interrupt controller (PIC). This circuit is responsible for producing a stop signal to be connected to the processor. This signal is activated when at least one unit asks to communicate with the processor. For each regional unit of the processor must perform different functions. Thus, the processor must know which unit requires service. For this reason, the programmable interrupt controller except the interrupt signal, and generates a number (usually 255) which gives the processor unit number input stops and must serve.
Figure 3.8.3 Connecting multiple units through PIC
Figure 3.8.3 shows the four devices connected to the processor via a programmable interrupt controller. Each device has two signals (INTR - INTA) which are connected to the interrupt controller. To first (INTR) is out and it asks for service. The second (INTA) is input and a response to INTR signal indicating that it has commenced the process of service.
The advantage of this technique is that it can serve very fast peripherals. Because the processor controls a very fast pace (in any order) the interrupt signal the device that wants to communicate with the processor does not wait at all and served almost immediately. Even the processor does not lose time to check if a module wants to communicate with him as to the method of polling. An audit performed by the processor for the signal is interrupted and the material does not remove valuable computing power of the processor.
The major disadvantages of this technique is that the design of computer systems become more complex, and the program becomes more complex processor.
3.8.3 Direct Memory Access
The technique of direct memory access (DMA - (Direct Memory Access) is a method of mass data transfer between peripherals and memory without CPU intervention.
This technique is usually used to transfer data from storage media to memory and vice versa, bypassing the CPU. For the implementation of this technique needs a controller DMA. This controller is an integrated circuit connected to the upper corridor of the computer system. When we direct memory access controller DMA instead of the CPU assumes control of the corridor.
Under this technique, when you want to transfer large amount of data from memory to input-output units and vice versa, the processor gives the appropriate information to the DMA controller. With this feedback, the DMA controller can perform data transfer without CPU intervention. The time it takes to transfer, the processor can perform other functions, thus increasing the efficiency of the computer system.
Figure 3.8.4 DMA Controller
The DMA controller has at least four registers. In these registers, the processor provides the information for transferring the data he wants to do. In an initial registrar is the memory address where data will be stored or read from it. In another register is the number of bytes to be transferred. In the third register the name of the input-output unit that will participate in the transfer. Finally, a fourth register is the direction of the data. So if you transfer data from memory to the peripheral unit or vice versa.
During the operation of the DMA controller to control the computer's route system is transferred from the processor controller DMA. Once the transfer of all data, the DMA controller gives in turn control the computer's route system to the processor. This mode provides faster data transfer and is called "Burst Transfer» (Burst Mode)
Another mode of the DMA controller is not taking control of the corridor from the editor. The data transfer time is only at times when the processor does not use the treadmill. This method of operation is called "cheating cycle» (Cycle Stealing) This function does not ensure faster data transfer but also ensures the simultaneous operation of the processor and a DMA data transfer.
The mode controller DMA, if that is used to transfer burst or cycle steal, depends on the speed of the peripherals. If the speed of the regional unit is about the same as the memory, the burst transfer is the best way. Because data transfer is the speed of memory the processor can not 'find' time in which the memory does not work. So if you interrupt the direct transfer of data would have delayed the service of fast peripherals. In a slow but transfer the processor finds time in which the memory does not work and can communicate with it and the memory. So for slow peripherals best way is that of cheating cycle. Finally, the choice of how the DMA controller is determined by the amount of data and how important is the transfer of such data.
What did you learn
There are two contact points of entry with the editor.
For slower devices use the technique for fast and Polling technique holiday.
With a DMA controller can transfer data from memory to input-output unit without processor intervention.
There are two modes DMA. The burst mode and o cycle stealing.
Terminology
Scan (Polling)
Burst Transfer (Burst Mode)
Cheating cycle (Cycle Stealing)
Direct memory access (DMA)
Stop (Interrupt)
Control knowledge
What technique is called polling;
What are the advantages and disadvantages of the technique polling;
For which devices are suitable technique holiday and why?
Data can be transferred in the corridor of a computer system without the intervention of the processor and if so how?
What kinds of DMA operation you know?
