Lesson 3.7o decoding circuits
Lesson 3.7o decoding circuits
Modern architecture calc. systems
Auxiliary circuits
Microcomputer system with many memories
By studying the lesson you will
to know how does the tri-state buffer
to know how a decoder
to design an address decoder circuit
3.7.1 Architecture of computer systems
In a computer system there are usually more than one memory module. Because the capacity of a single integrated is small and the large memory requirement, in many computer systems use integrated memory. Even if we use different types of memory in a system necessarily use a lot of integrated memory.
The number of different addresses that can access a processor, as already mentioned, depends on the number of forming the bit address.
Take for example a computer system comprising a processor 16-bit that can access 216 = 65 536 different locations ie 64KBytes. Suppose we have a memory and ROM 32Kbytes RAM 32Kbytes. Suppose the ROM memory must be selected addresses from 0 to 32767 and the RAM addresses from 32768 to 65535.
Assume we have an integrated RAM and a ROM memory 32Kbytes in size each. Figure 3.7.1 is a part of the treatment plan.
Figure 3.7.1 Processing Department
Each of the two memory size is 32Kbytes. Since each memory size is 32Kbytes (215 = 32KV) requires 15 address lines (A0-A14). The computer system has 16 address lines and needs a circuit to make the right choice of memory, depending on the direction he wants to read or write to the editor.
If we had a computer system memory size 64Kbytes, then we would not have the problem of choice of memory, each address signal processor will be connected to signals of memory. The choice of the location of memory, as we have said in previous lessons, making the circuit of an internal memory.
In the case of our example, we have more than a memory, we have the problem of the choice of integrated memory. That is to complete what is the address that wants to access the processor. The computer systems have an address decoding circuit, with the help of which respectively selected the integrated memory.
In our example, the decoding circuitry only needs to choose one of the two memories. Looking at Table 3.7.1, we see that the more value bit (MSB) of the address is 0 when the address is from 0 to 32767 and 1 when the address is 32768 to 65535. With this observation we can design the circuit of the decoder consists of only one inverter.
Table 3.7.1 Signals Directorate
Addresses
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Memory
0 1 2 to 32767
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
until
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ROM
32768
32769
32770
until
65535
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
until
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RAM
As shown in Figure 3.7.2 the signal connects to the A15 (Chip Select) of ROM memory and the output of the inverter is connected to the RAM.
Figure 3.7.2 Connecting two memories in a computer system
On the signal each completed we can choose or not. So when the A15 is '0 'then the ROM is '0' and RAM '1 'and have the option ROM. While if the A15 is '1 'then the ROM is '1' and the RAM is '0 'and have a choice of RAM.
3.7.2 Auxiliary circuits
Each integrated corridor that connects to computer system must meet the following conditions:
Be has an active low enable signal, usually called
Have special buffers, called tri-state buffers (three state buffers). The outputs are integrated in the hallway of the data only through these buffers.
The term we mean that an active low when the signal is logical 0 to be activated when it is complete and '1 'is the integrated disabled.
Figure 3.7.3 shows the schematic representation of a tri-state buffer. As mentioned in a previous lesson, all connected to the integrated data path must have output buffers in three state. This is required not to affect the outputs of integrated, that is not selected, the signals of the data path. The three state buffer has a capacity, when the control signal is disabled, the output is disconnected completely from the resulting entry in the logical level does not at all influenced by the level of the input signal. Otherwise, where the control signal is activated the output is connected to the input and the line of the runway is occupied by the exit ramp. Specific buffers are so named because they are three states in the exit (1, 0, high resistance).
Figure 3.7.3 Isolator three states (three state buffer)
In the case of memory, where data signals are bi-directional, each pin has a pair of tri-state buffer as shown in Figure 3.7.4. This is true with other integrated bi-directional data and related data on a treadmill.
Figure 3.7.4 Pair tri-state buffer
The control signal input in play when it has taken complete command to read data. In this case the control signal output must be disabled to prevent a conflict of data.
The control signal output is enabled only when the integrated command has taken to provide data.
The choice of when you connect an integrated onto the runway of data is done by a decoding circuit. This circuit takes as input the address and gives the output for each chip.
The selection is done with the help of the decoder is a logical circuit. The entrance receives a binary number, even with the number n bits. The output is the number of signals.
For example, let's consider a decoder that has its input signals 3. The exit must have 8 marks. Figure 3.7.5 shows the schematic of the decoder.
Figure 3.7.5 Schematic decoder
For each logical channel can see the operation, with a table showing the costs affordable for all values of the inputs. Such a table is called the truth table. Table 3.7.2 shows the truth table of the decoder 3 to 8.
Table 3.7.2 Table of truth decoder 3 to 8
INPUTS
OUTPUTS
I2 i1 I0
d0 d1 d2 d3 d4 d5 d6 d7
0 0 0 1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
1
The outputs d0-d7 have a value depending on the combination of the input price of i0-i2. We observe that for each combination of only one output is 1, that corresponds to the binary input. For example when I i2i1i0 = 000 only the output is 1 d0. When I i2i1i0 = 101 d5 only the output is 1 and the end when we i2i1i0 = 111 d7 = 1
Typically, the circuits outputs d0-d7 are in an inverted form. So we have as output signals. The reason is that if we want to lead with these other CS integrated which need to be inverted we ready.
3.7.3 Computer system with many memories
Suppose we have a computer that has a strip width 16 addresses. The total memory that can be accessed by the processor is 64Kbytes. In our system we want to have memories and ROM memory RAM. The total size of ROM suppose is 16Kbytes and 32Kbytes RAM. Table 3.7.3 shows the address you want to be occupied by these memories.
Table 3.7.3 Distribution of memories
Addresses (IECH)
Addresses (decimal)
Type
0000-1FFF
0000-8191
RAM
2000-5FFF
8192-24575
ROM
8000-9FFF
32768-40959
RAM
C000-FFFF
49152-65535
RAM
Each integrated memory that we will use a size 8Kbytes. So we will need two ROM memories and memories of four RAM. To facilitate understanding, we form the table of system memory. Table 3.7.4 is 64Kbytes of memory divided into segments of 8Kbytes.
Table 3.7.4 Table memory computer system
Addresses (IECH)
Addresses (decimal)
Memory
0000-1FFF
0000-8191
RAM 1
2000-3FFF
8192-16383
ROM 1
4000-5FFF
16384-24575
ROM 2
6000-7FFF
24576-32767
Not used
8000-9FFF
32768-40959
RAM 2
A000-BFFF
40960-49151
Not used
C000-EFFF
49152-57343
RAM 3
E000-FFFF
57344-65535
RAM 4
For each part used will include an integrated memory corresponding type.
The number of lines in each memory address is 13. This is, as mentioned in previous lessons, the type 213 = 8192 = 8 * 1024 = 8Kbytes. The decoding circuitry must select one of the 6 memory address according to what wants to communicate with the processor.
For the circuit design of decoding should be noted, as was the simple example at the beginning of the course, the areas of memory. So for example, the first region from 000016 to 1FFF16 observe that the higher value 3 bits remain constant and equal to 0 and change only the lower 13 bits value. For the third region 400016 5FFF16 to the three higher-value bits are again stable and equal to 010. As a general observation we see that each part of the 8 memory characterized by the three highest value bits, as shown in Table 3.7.5, which remain constant throughout the area of memory and change only the value of least 13 bits.
Table 3.7.5 Signals decoding
Memory Areas
A15
A14
A13
A12-A0
Memory
0000-1FFF
0
0
0
X
RAM 1
2000-3FFF
0
0
1
X
ROM 1
4000-5FFF
0
1
0
X
ROM 2
8000-9FFF
1
0
0
X
RAM 2
C000-DFFF
110X
RAM 3
E000-FFFF
1
1
1
X
RAM 4
So as a criterion for selection of memories we can get the price of these three bits of the track address (A15-A14-A13). The selection signals (Chip Select) memories can be produced by a decoder 3 to 8.
Figure 3.7.6 seems part of a computer system. Shows the processor address along the corridor, and the integrated memory. Finally, the decoder 3 shown in 8. The three higher-value bits of the address led only to the decoder. The remaining 13 address signals are 13 signals in each direction of integrated memory.
Each output of the decoder is now a group of 8196 memory locations, ie integrated memory which should be chosen. That is, the decoder output signal is the choice of memories. The decoder at the output of activated each time a single signal. This results in two or more memories never selected simultaneously, so you do not have collision data.
The D0 output of the decoder will be activated when we have the entrance to the decoder "000". This means that we address in the memory area from 0000 to 1FFF. The same goes for the other outputs of the decoder and the correlation shown in Table 3.7.6.
Table 3.7.6 Mapping signal decoder with memory areas
0000-1FFF
D0
RAM 1
2000-3FFF
D1
ROM 1
4000-5FFF
D2
ROM 2
6000-7FFF
D3
X
8000-9FFF
D4
RAM 2
A000-BFFF
D5
X
C000-DFFF
D6
RAM 3
E000-FFFF
D7
RAM 4
As shown in Figure 3.7.6 the signal D3 and D5 of the decoder are not linked to any memory because unused memory in their respective areas.
Figure 3.7.6 Circuit six computer memory system
What did you learn
In a computer system there are more than a memory having the address decoding circuitry
Each integrated corridor that connects to computer system must enable signal is active low and tri-state buffers
The tri-state buffer allows or not with a control signal to connect to an output data path.
The decoding circuitry of a computer system determines which integrated selected to log onto the runway.
Terminology
Tri-state buffer (Three state buffer)
Decoder
Low active signal (active-low signal)
Truth table
Control knowledge
What we call an active low signal?
What is a tri-state buffer?
What is the truth table?
Give the truth table of a decoder 2 to 4 and a 4 to 16.
Design a circuit that uses memory ROM and RAM size 8Kbytes areas for 0000-7FFF (ROM) and 8000-FFFF (RAM).
