Lesson 3.6o Memory Functions
Lesson 3.6o Memory Functions
Reading Memory
Register memory
Cache
By studying the lesson you will
to know the functions are for reading a memory location.
to know the functions required for a given record to a memory location.
Knowing what is cached.
Knowing the function and usefulness of the cache in a computer system.
3.6.1 Reading Memory
For a memory read operation must address signals, data and control signals to get proper values at specific times. These times are different from memory to memory and is typical for memory speed.
The simple operation of reading the memory is in four steps:
1.The entrance of the memory address takes the value of the address we want to read.
2.Energopoieitai the memory selection signal CS (chip select).
3.The contents of memory location, selected, as appears in the output data lines of the memory.
4.Oloklirosi read as
Figure 3.6.1 shows the timing diagram of a static memory, showing the intervals that are characteristic of the mode of reading.
The process of reading begins from the moment we are implementing the management. The memory takes some time to do the decoding of the address and determine the memory location we want to read. Then, the selection signal (Chip Select (CS) position data that appear in the output.
The time from the moment we choose the direction we want to read, until the moment that the data of the memory location of data in rows called access time.
Figure 3.6.1 Timing diagram read cycle
Time selection is called the time it takes to display position data memory from the moment you energopoithei signal chip select.
The access time is always greater than the time because they have first option to apply the address and then reactivate the memory.
The memory keeps the data in the output as long as the address remains constant and the memory is enabled. The minimum time between two successive readings of different memory locations called cycle time reading, and is typical of the speed of memory. It shows us how fast we can read data. For example if we reading 10nsec cycle time to 1 sec, then we can read 100 million memory locations.
3.6.2 Memory Register
The key steps to be taken to a record as a memory location are:
1.Dinetai the address where you want to write.
2.Epilegetai memory by activating the chip select.
3.The input data takes the value we want to write.
4.Energopoieitai registration process with the signal WE (write enable)
5.The record is complete and can begin a new recording or reading.
Figure 3.6.2 shows the timing diagram of a static memory recording.
The record data to memory begins when activated signal write enable (WE). The activation of this signal should be passed after a period when applied at the record. This period is needed to determine the memory location called the delay time enrollment (tAW).
The registration process begins with the implementation of the address we want to write and activation of the signal memory chip select. Then we must apply the data we want to write and keep them stable. The time required to retain the data consistently called timing data and denoted tDW.
Figure 3.6.2 Timing diagram enrollment cycle
Each memory takes some time to complete your registration data and can start a new cycle read or write. The sum of the years needed for these five steps is called cycle time recording. (TWCY). It is a typical speed of memory because it shows that last year a record.
3.6.3 Cache
The speed of a computer system depends largely on the speed of memory. As quickly as possible to read and write to memory faster running programs in a computer system. However, the use fast main memory can not be made because the cost of the computer system would be very high.
To increase the speed of the computer system used a fast memory that is physically much smaller in size than the main memory. In this memory we keep a copy of a small section of main memory. This memory called cache (cache memory) inserted in the movement of data between the processor and main memory, as shown in Figure 3.6.3.
Figure 3.6.3 Location Cache
The cache is divided into groups of memory locations called lines (cache line). For example, a line can be composed of 16 memory locations. Each line is a copy of the 16 seats in the main memory that is adjacent to the main memory as shown in Figure 3.6.4.
Figure 3.6.4 Organization cache
Suppose now that the processor wants to read a data from one memory address even the 37. Then are these steps:
Check that the address 37 is in cache.
Suppose 4 is in the cache line, as shown in Fig. Then the reading is done from the cache without accessing the relatively slower main memory.
If not found, then the reading is done from memory. At the same time the 15 adjacent memory locations, along with the address read, copied to a cache line. The reason is that we expect to be followed by other readings from neighboring places. So the next steps in the readings that follow will be from the cache, which is faster.
When readings are made from many pieces of the processor from main memory is copied to the cache lines until you fill all the lines. When you need to transfer a piece of memory in cache already filled then you have at least one cache line to be deleted. There are two techniques commonly applied in the selection of the line should be deleted.
Delete based on retention time (FIFO first in - first out). According to this technique, the line has remained in the cache longer be deleted. That deletes the oldest record time.
Delete based on less use
(LRU - least recently used). According to this technique, the line will be removed is that which is left unused longer than others. So an old record is not deleted often used in contrast with the previous technique.
If the processor wants to write to memory distinguish two cases:
If the address you want is just to write to main memory and not in cache, then the record is done properly.
If the given address we want to write is in cache, then record only the main memory will create disagreement with the occult. To overcome this problem, use one of the following techniques:
Diengrafis (write throught). According to this technique is the recording simultaneously in main memory and cache. So there is no main memory and cache have different prices.
Rewritable (write on). With the method of rewriting the record only in cache. The contents of main memory is not updated until you need to delete the word from the cache.
The effectiveness of the cache based on the fact that programs are running a processor capacity, readings and references to memory are not in random directions, but in neighboring and nearby locations between them. This is called locality of reference of the programs. The end result is that the readings and recordings of memory be made to the speed of the cache rather than the slow main memory.
With the development of technology of memory and increasing speed and storage density has become possible to use most two cache levels.
The first level cache (level 1) is integrated into the processor. This memory is faster. He works with processor speed
The second level cache (level 2) in the previous processor technology is on a separate circuit than the processor. In modern processors, however, and the second level cache, and of course the first level is built on the same integrated processor. The two levels of cache further improves the speed of movement (Entries - reading) data from the memory.
What did you learn
The operation of reading a memory location is in four main steps.
For reading memory first select the memory location we want to read, then activate the memory and then read the contents of memory.
The operation of recording a memory location is in 5 basic steps
To register select a memory location to location and activate the memory. After the data that we want to write and activate the signal recording memory. Finally, the memory writes data to the position we have chosen.
The cache is a buffer between the processor and main memory. This store recent memory locations used by the processor.
Terminology
Access time - choice - read cycle
Delay write - application data - recording cycle
Cache
Diengrafi
Rewrite
Locality of reference
Control knowledge
1.Poia are the basic steps of reading a memory?
2.What is called cycle time reading?
3.Ti call time data application and what cycle time recording?
4.Ti called cache?
5.Poies are scheduled to delete a word of the cache?
6.Me how the contents of main memory and cache are in agreement?
