Logic gates and truth tables
pages 15-20
1.3 LOGICAL GATES
1.3.1 Logic diagrams of logic gates
The logic gates are the basic building blocks for digital circuits. As we have in building the bricks and walls are constructed using complex structures and similar material again and again, so in the digital circuits using logic gates to construct complex circuits.
The logic gates one and two entries in Table 1.3.1 where the output is expressed as a function of income.
Table 1.3.1
Logic Gates - Functions
Logic gate
Inputs
Output
Function
Buffer buffer
A
Y
Y = A
Inverter NOT
A
Y
Y =
AND
A, B
Y
Y = A · B
OR
A, B
Y
Y = A + B
NAND
A, B
Y
Y =
NOR
A, B
Y
Y =
XOR
A, B
Y
Y = A · + · B = AÅB
XNOR
A, B
Y
Y = A · B + · == A ¤ B
The flowchart (symbolism) of the gates are presented in Table 1.3.2.
Table 1.3.2
Logic Gates - Logic Diagrams
Logic gate
Logical Diagram
A
Y = A
Buffer buffer
Y =
A
Inverter NOT
A
B
Y = A · B
AND
A
B
Y = A + B
OR
Y =
A
B
NAND
A
B
Y =
NOR
A
B
Y = AÅB
XOR
A
B
Y = A ¤ B
XNOR
1.3.2 Tables truth of logic gates
The buffer (buffer)
O buffer (buffer) is a gate with one input and one output is equal to the input.
The function of the buffer is:
Y = A
and the truth table of the buffer is shown in Table 1.3.3.
Table 1.3.3
Truth table of the buffer
A
Y = A
0
0
1
1
The NOT gate
The NOT gate has one input and one output is equal to the complement of the input.
The function of the gate is NOT:
and the truth table of the NOT gate is shown in Table 1.3.4.
Table 1.3.4
Truth table of the NOT gate
A
0
1
1
0
The AND gate
The AND gate has two inputs and one output is "1" if both inputs are "1".
The function of the gate AND is:
Y = A · B
and the truth table of AND gate is shown in Table 1.3.5.
Drank 1.3.5
Truth table of AND gate
A
B
Y = A · B
0
0
0
0
1
0
1
0
0
1
1
1
The OR gate
The OR gate has two inputs and one output is "1" if at least one of the two inputs are "1".
The function of the OR gate is:
Y = A + B
and the truth table of OR gate is shown in Table 1.3.6.
Drank 1.3.6
Truth table of OR gate
A
B
Y = A + B
0
0
0
0
1
1
1
0
1
1
1
1
The NAND gate
The NAND gate results from an AND gate followed by a gate NOT. The NAND gate has two inputs and one output is "1" if at least one of the two inputs are "0".
The function of the NAND gate is:
and the truth table of NAND gate shown in Table 1.3.7.
Drank 1.3.7
Truth table of NAND gate
A
B
0
0
1
0
1
1
1
0
1
1
1
0
The NOR gate
The NOR gate results from an OR gate followed by a gate NOT. The NOR gate has two inputs and one output is "1" if both inputs are "0".
The function of the NOR gate is:
and the truth table of NOR gate is presented in Table 1.3.8.
Drank 1.3.8
Truth table of NOR gate
A
B
0
0
1
0
1
0
1
0
0
1
1
0
The XOR gate
The gate XOR (exclusive OR) has two inputs and one output is "1" if both inputs are different (this is also called the gateway dispute or comparison).
The function of the XOR gate is:
Y = AÅB = A · + · B
and the truth table of XOR gate is shown in Table 1.3.9.
Drank 1.3.9
Truth table of XOR gate
A
B
Y = AÅB
0
0
0
0
1
1
1
0
1
1
1
0
The XNOR gate
The gate XNOR (exclusive NOR) has two inputs and one output is "1" if both inputs are equal.
The function of the XNOR gate is:
Y = A ¤ B = A · B + ·
and the truth table of XNOR gate is shown in Table 1.3.10.
Drank 1.3.10
Truth table of XNOR gate
A
B
Y = A ¤ B
0
0
1
0
1
0
1
0
0
1
1
1
1.3.3 Reasonable multiple entry gates
The two entrance gates can be expanded to have more than two inputs, if their actions are commutative and distributive properties. The implementation of such a gate three (3) Entry gates using two identical (2) inputs shown in Figure 1.3.1.
Figure 1.3.1
Technical input expansion
if the gate is commutative and distributive property
For example, an AND gate three inputs can be implemented using two AND gates of two inputs as shown in Figure 1.3.2, as applicable:
- The commutative property
Y = A · B = B · A
- The status prosetairistiki
Y = A · B · C = (A · B) · C = A · (B · C)
Figure 1.3.2
Implementation of AND gate three entrance
AND gates with two inputs
By the same token, a three input OR gate can be implemented using two OR gates of two inputs as shown in Figure 1.3.3.
Figure 1.3.3
Implementation of three input OR gate
OR gates with two inputs
The three input NAND gate is defined as the complement of the AND gate three entrances. Therefore, the output of NAND gate three inputs are "1" if at least one of the two inputs are "0".
A NAND gate three inputs can be implemented using two NAND gates of two inputs, it is the commutative property, but does not apply property prosetairistiki after:
as shown in Table 1.3.11.
Table 1.3.11
Gate NAND: does not apply property prosetairistiki
A
B
C
0
0
0
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
1
1
0
1
1
1
0
1
1
By the same token, a NOR gate three inputs can be implemented using two NOR gates of two inputs.
The logic of extending the number of inputs of the gates can be applied to four input gates.
For example, an AND gate four inputs can be implemented using AND gates three and a two input OR gate four inputs can be implemented using three two OR gates entrances.
