Θεόδουλος Λιοντάκης

Δάσκαλος Πληροφορικής ΠΕ86

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I  redesigned the add/subtract unit from VHDL to schematic.

Add/Sub signals choose the operation between 8 or 16 bit numbers X,Y,carry(cin) size depent on "half" signal.

Result in Z and carry (cout), neg, overflow, zero

 

Update 15/5/2017

Added carry look ahead logic for faster operations. Although it's just 2-bit/stage to keep the complexity low it decreased the operation time from 3 to 2 cycles.

24/5/17 fixed a bug