I am very pleased today (26/10/2017) because I replaced the VHDL register array with my implementation in schematic.
This reduced the used logical elements for all the system from 6150 to 4900 and in the same time increased the registers from 5 to 8 with only a small penalty in speed.
So now registers A0 to A7 are available.
27/10/2017 Added second output stage allowing 2 simultaneous reads of registers.
Signal Ai[0..15] is the input that when Wen is high, it is stored to the register pointed by R[0..2].
Half is defining if the operation is byte or word wide.
Signals Ao[0..15], Ao2[0..15] are the outputs that have the values of registers pointed by R[0..2], RR[0..2]
The schematic follows:
